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engineering specification type 15.0 uxga color tft/lcd module model name:itux97h document control number : oem i-97h-03 note:specification is subject to change without notice. consequently it is better to contact to international display technology before proceeding with the design of your product incorporating this module. sales support international display technology engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 1/34
i contents i contents ii record of revision 1.0 handling precautions 2.0 general description 2.1 characteristics 2.2 functional block diagram 3.0 absolute maximum ratings 4.0 optical characteristics 5.0 signal interface 5.1 connectors 5.2 interface signal connector 5.3 interface signal description 5.4 interface signal electrical characteristics 5.4.1 signal electrical characteristics for lvds receiver 5.4.2 lvds receiver internal circuit 5.4.3 recommended guidelines for motherboard pcb design and cable selection 5.5 inverter signal connector 5.6 inverter signal description 5.7 inverter signal electrical characteristics 6.0 pixel format image 7.0 interface timings 7.1 timing characteristics 7.2 timing definition 8.0 power consumption 9.0 power on/off sequence 10.0 mechanical characteristics 11.0 national test lab requirement engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 2/34
ii record of revision to update inverter signal electrical characteristics. to update luminance versus smbus data. 23 24 oem i-97h-03 february 1,2002 to update backlight power consumption. to add min. value of white luminance. to update electrical specifications and dimming. to update the luminance versus the smbus data. 6 9 23 24 oem i-97h-02 december 10,2001 first edition for customer. based on internal specification ec f79204 as of september 7,2001. to adopt a "burst mode inverter". all oem i-97h-01 october 30,2001 summary page document revision date engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 3/34
1.0 handling precautions 1) since front polarizer is easily damaged, pay attention not to scratch it. 2) be sure to turn off power supply when inserting or disconnecting from input connector. 3) wipe off water drop immediately. long contact with water may cause discoloration or spots. 4) when the panel surface is soiled, wipe it with absorbent cotton or other soft cloth; do not use solvents or abrasives. 5) since the panel is made of glass, it may break or crack if dropped or bumped on hard surface. 6) since cmos lsi is used in this module, take care of static electricity and insure human earth when handling. 7) do not open nor modify the module assembly. 8) do not press the reflector sheet at the back of the module to any directions. 9) in case if a module has to be put back into the packing container slot after once it was taken out from the container, do not press the center of the cfl reflector edge. instead, press at the far ends of the cfl reflector edge softly. otherwise the tft module may be damaged. 10) at the insertion or removal of the signal interface connector, be sure not to rotate nor tilt the interface connector of the tft module. 11) after installation of the tft module into an enclosure ( notebook pc bezel, for example), do not twist nor bent the tft module even momentary. at designing the enclosure, it should be taken into consideration that no bending/twisting forces are applied to the tft module from outside. otherwise the tft module may be damaged. 12) the fluorescent lamp in the liquid crystal display (lcd) contains mercury. do not put it in trash that is disposed of in landfills. dispose of it as required by local ordinances or regulations. 13) small amount of materials having no flammability grade is used in the lcd module. the lcd module should be supplied by power complied with requirements of limited power source (2.11, iec60950 or ul1950), or be applied exemption conditions of flammability requirements (4.4.3.3, iec60950 or ul1950) in an end product. 14) never apply detergent or other liquid directly to the screen. the information contained herein may be changed without prior notice. it is therefore advisable to contact international display technology before proceeding with the design of equipment incorporating this product. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by international display technology for any infringements of patents or other right of the third partied which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of international display technology or others. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 4/34
2.0 general description this specification applies to the type 15.0 color tft/lcd module 'itux97h'. this module is designed for a display unit of notebook style personal computer. the screen format and electrical interface are intended to support the uxga (1600(h) x 1200(v))screen. support color is native 262k colors ( rgb 6-bit data driver ). all input signals are lvds interface compatible.this module contains an inverter card for backlight. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 5/34
2.1 characteristics the following items are characteristics summary on the table under 25 degree c condition: 0 to +50 -20 to +60 temperature range (degree c) operating storage (shipping) native 262k colors ( rgb 6-bit data driver ) support color panel ids,smb_clk,smb_dat,fpvee electrical interface (inverter) 6-bit digital video for each color r/g/b, 3 sync, clock (8 pairs lvds) electrical interface (logic) 317.3(w) x 242.0(h) x 11.2(d) typ.11.5(d)max. physical size [mm] 665 typ. 700 max. weight [grams] 5.6 typ. backlight power consumption [watt] pwr_src=14.4v smdata=00h 2.4 typ. 3.4 max. logic power consumption [watt] +3.3 typ. +5.0 typ. +14.4 typ. nominal input voltage [volt] vdd 5vsus,5valw line pwr_src line 30typ., 50max.(each) optical rise time/fall time [msec] 200 : 1 typ. contrast ratio 150 typ.(center) 140 typ.(5 points average) typical white luminance [cd/m 2 ] smdata=00h: normally white display mode r.g.b. vertical stripe pixel arrangement 0.1905(per one triad) x 0.1905 pixel pitch [mm] 1600(x3) x 1200 pixels h x v 304.8(h) x 228.6(v) active area [mm] 381 screen diagonal [mm] specifications items engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 6/34
2.2 functional block diagram the following diagram shows the functional block of the type 15.0 color tft/lcd module. the first lvds port transmits even pixels while the second lvds port transmits odd pixels. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 7/34 j a e f i - x b 3 0 s - h f 1 0 ( 3 0 p i n ) x-driver tft array/cell 6bit color data for r/g/b dtclk(even/odd) dsptmg hsync vsync vdd lcd controller lcd drive card backlight unit 1600(r/g/b) x 1200 gnd dc-dc converter ref circuit (even/odd) < 8 pairs lvds > even pixel odd pixel dual lvds receiver lcd-drive connector y-driver g/a i n v e r t e r c o n n e c t o r m o l e x 5 2 2 0 7 - 1 6 9 0 ( 1 6 p i n ) panel idsp smb_clk smb_dat fpvee pwr_src 5vsus 5valw gnd inverter clk eedid data eedid v eedid eedid chip
3.0 absolute maximum ratings absolute maximum ratings of the module is as follows : rectangle wave g ms 50 18 shock g hz 1.5 10-200 vibration note 1 %rh 95 5 hst storage humidity note 1 deg.c +60 -20 tst storage temperature note 1 %rh 95 8 hop operating humidity note 1 deg.c +50 0 top operating temperature v +7 -1 smb_clk smb_dat v +5.5 -0.3 fpvee v +vdd+0.3 -0.3 vin input voltage of signal v +25 -0.3 pwr_src v +5.5 -0.3 5vsus, 5valw v +4.0 -0.3 vdd supply voltage conditions unit max min symbol item note 1 : maximum wet-bulb should be 39 degree c and no condensation . engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 8/34
4.0 optical characteristics the optical characteristics are measured under stable conditions as follows under 25 degree c condition : 120 min. (center) 112 min. (5 points average) 150 (center) 140 (5 points average) white luminance (cd/m 2 ) smdata=00h - 0.329 white y - 0.313 white x - 0.132 blue y - 0.149 blue x - 0.544 green y - 0.312 green x (cie) - 0.332 red y chromaticity - 0.569 red x color 50 max. 30 falling (ms) 50 max. 30 rising response time 100 min. 200 contrast ratio - - 15 30 vertical (upper) k 10 (lower) k:contrast ratio - - 40 40 horizontal (right) k 10 (left) viewing angle (degrees) note typ. specifiation conditions item engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 9/34
5.0 signal interface 5.1 connectors physical interface is described as for the connector on module. these connectors are capable of accommodating the following signals and will be following components. fi-x30m mating type / part number fi-xb30s-hf10 type / part number jae manufacturer for signal connector connector name / designation (fpc) mating type / part number 52207-1690 type / part number molex manufacturer for inverter connector connector name / designation engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 10/34
5.2 interface signal connector fg ( gnd ) 32 rein2+ 16 roclkin+ 31 rein2- 15 roclkin- 30 gnd 14 gnd 29 rein1+ 13 roin2+ 28 rein1- 12 roin2- 27 gnd 11 gnd 26 rein0+ 10 roin1+ 25 rein0- 9 roin1- 24 data eedid ( note 2 , 4 ) 8 gnd 23 clk eedid ( note 2 , 4 ) 7 roin0+ 22 nc ( reserved , note 1 ) 6 roin0- 21 v eedid ( note 2 , 3 ) 5 gnd 20 vdd 4 reclkin+ 19 vdd 3 reclkin- 18 gnd 2 gnd 17 fg ( gnd ) 1 s i g n a l n a m e pin # s i g n a l n a m e pin # note: 1. 'reserved' pins are not allowed to connect any other line. 2. this lcd module complies with "vesa enhanced extended display identification data standard release a, revision 1" and supports "eedid version 1.3". this module uses serial eeprom br24c02fv (rohm) or compatible as a eedid function. 3. v eedid power source shall be the current limited circuit which has not exceeding 1a. (reference document : "enhanced display data channel (e-ddc tm ) proposed standard", vesa) 4. both clk eedid line and data eedid line are pulled-up with 10k ohm resistor to v eedid power source line at lcd panel, respectively. voltage levels of all input signals are lvds compatible (except vdd,eedid). refer to "signal electrical characteristics for lvds(*)", for voltage levels of all input signals. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 11/34
5.3 interface signal description frame ground fg 32 positive lvds differential clock input (odd) roclkin+ 31 negative lvds differential clock input (odd) roclkin- 30 ground gnd 29 positive lvds differential data input (odd b2-b5) roin2+ 28 negative lvds differential data input (odd b2-b5) roin2- 27 ground gnd 26 positive lvds differential data input (odd g1-g5, b0-b1) roin1+ 25 negative lvds differential data input (odd g1-g5, b0-b1) roin1- 24 ground gnd 23 positive lvds differential data input (odd r0-r5, g0) roin0+ 22 negative lvds differential data input (odd r0-r5, g0) roin0- 21 ground gnd 20 positive lvds differential clock input (even) reclkin+ 19 negative lvds differential clock input (even) reclkin- 18 ground gnd 17 positive lvds differential data input (even b2-b5, hsync, vsync, dsptmg) rein2+ 16 negative lvds differential data input (even b2-b5, hsync, vsync, dsptmg) rein2- 15 ground gnd 14 positive lvds differential data input (even g1-g5, b0-b1) rein1+ 13 negative lvds differential data input (even g1-g5, b0-b1) rein1- 12 ground gnd 11 positive lvds differential data input (even r0-r5, g0) rein0+ 10 negative lvds differential data input (even r0-r5, g0) rein0- 9 eedid data data eedid 8 eedid clock clk eedid 7 reserved reserved 6 eedid 3.3v power supply v eedid 5 +3.3v power supply vdd 4 +3.3v power supply vdd 3 ground gnd 2 frame ground fg 1 description signal name pin # note: 1. input signals of odd and even clock shall be the same timing. 2. the module uses a 100ohm resistor between positive and negative data lines of each receiver input. 3. even: first pixel , odd: second pixel engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 12/34
eedid data data eedid eedid clock clk eedid eedid 3.3v power supply v eedid ground gnd power supply vdd horizontal sync: this signal is synchronized with dtclk. both active high/low signals are acceptable. hsync (h-s) vertical sync: this signal is synchronized with dtclk. both active high/low signals are acceptable. vsync (v-s) when the signal is high, the pixel data shall be valid to be displayed. +dsptmg (dsp) the signal is used to strobe the pixel +data and the +dsptmg (even/odd) data clock: the typical frequency is 81mhz. dtclk blue-pixel data: each blue pixel's brightness data consists of these 6 bits pixel data. (even/odd) blue data 0 (lsb) +blue 0 (eb0/ob0) blue data 1 +blue 1 (eb1/ob1) blue data 2 +blue 2 (eb2/ob2) blue data 3 +blue 3 (eb3/ob3) blue data 4 +blue 4 (eb4/ob4) blue data 5 (msb) +blue 5 (eb5/ob5) green-pixel data: each green pixel's brightness data consists of these 6 bits pixel data. (even/odd) green data 0 (lsb) +green 0 (eg0/og0) green data 1 +green 1 (eg1/og1) green data 2 +green 2 (eg2/og2) green data 3 +green 3 (eg3/og3) green data 4 +green 4 (eg4/og4) green data 5 (msb) +green 5 (eg5/og5) red-pixel data: each red pixel's brightness data consists of these 6 bits pixel data. (even/odd) red data 0 (lsb) +red 0 (er0/or0) red data 1 +red 1 (er1/or1) red data 2 +red 2 (er2/or2) red data 3 +red 3 (er3/or3) red data 4 +red 4 (er4/or4) red data 5 (msb) +red 5 (er5/or5) description signal name note: output signals except v eedid ,clk eedid and data eedid from any system shall be hi-z state when vdd is off . engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 13/34
5.4 interface signal electrical characteristics 5.4.1 signal electrical characteristics for lvds receiver the lvds receiver equipped in this lcd module is compatible with ansi/tia/tia-644 standard. electrical characteristics vth - vtl = 200mv mv +50 -50 vcm common mode voltage offset vth - vtl = 200mv v | vid | 2.4 - 2 | vid | 0.825+ 2 vcm common mode voltage mv 600 100 |vid| magnitude differential input voltage vcm=+1.2v mv -100 vtl differential input low threshold vcm=+1.2v mv +100 vth differential input high threshold conditions unit max typ min symbol parameter note: input signals shall be low or hi-z state when vdd is off. all electrical characteristics for lvds signal are defined and shall be measured at the interface connector of lcd (see " measurement system "). voltage definitions engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 14/34
measurement system engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 15/34
switching characteristics ps/clk 20 tcjavg cycle modulation rate (note 4) fc = 66.4mhz, tsu=thd=880ps ps +150 -150 tccj cycle-to-cycle jitter (fpt mode) (note 3) fc = 81mhz, tsu=thd=720ps ps +150 -150 tccj cycle-to-cycle jitter (note 3) ps 600 thd data hold time (fpt mode) (note 2) fc = 66.4mhz, tccj < 50ps, vth-vtl = 200mv, vcm = 1.2v, vcm = 0 ps 600 thd data setup time (fpt mode) (note 2) ps 500 thd data hold time (note 2) fc = 81mhz, tccj < 50ps, vth-vtl = 200mv, vcm = 1.2v, vcm = 0 ps 500 tsu data setup time (note 2) ns 16.4 15.1 14.5 tc cycle time (fpt mode) ns 13.3 12.3 12.0 tc cycle time mhz 69.0 66.4 61.0 fc clock frequency (fpt mode) mhz 83.0 81.0 75.0 fc clock frequency conditions unit max typ min symbol parameter note 1: all values are at vdd=3.3v, ta=25 degree c. note 2: see " timing definition " and " timing definition(detail a) " for definition. note 3: jitter is the magnitude of the change in input clock period. note 4: this specification defines maximum average cycle modulation rate in peak-to-peak transition within any 100 clock cycles. this specification is applied only if input clock peak jitter within any 100 clock cycles is greater than 300ps. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 16/34
timing definition (even port) engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 17/34
timing definition (odd port) engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 18/34
timing definition(detail a) note: tsu and thd are internal data sampling window of receiver. trskm is the system skew margin; i.e., the sum of cable skew, source clock jitter, and other inter-symbol interference, shall be less than trskm. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 19/34
5.4.2 lvds receiver internal circuit below figure shows the internal block diagram of the lvds receiver. this lcd module equips termination resistors for lvds link. cycle modulation rate 5.4.3 recommended guidelines for motherboard pcb design and cable selection following the suggestions below will help to achieve optimal results. use controlled impedance media for lvds signals. they should have a matched differential impedance of 100ohm. match electrical lengths between traces to minimize signal skew. isolate ttl signals from lvds signals. for cables, twisted pair, twinax, or flex circuit with close coupled differential traces are recommended. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 20/34
5.5 inverter signal connector pwr_src 16 smb_dat 8 pwr_src 15 smb_clk 7 pwr_src 14 fpvee 6 gnd 13 nc 5 gnd 12 panel-id3 4 gnd 11 panel-id2 3 5vsus 10 panel-id1 2 5valw 9 panel-id0 1 (note*) signal name pin # signal name pin # (note*) molex connector no.1 mark engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 21/34
5.6 inverter signal description this power rail should be used as a power rail to drive the backlight dc-ac converter (9v to 21v) typ pwr_src 16 this power rail should be used as a power rail to drive the backlight dc-ac converter (9v to 21v) typ pwr_src 15 this power rail should be used as a power rail to drive the backlight dc-ac converter (9v to 21v) typ pwr_src 14 gnd 13 gnd 12 gnd 11 this should be used as power source for the control circuitry on the inverter. 4.85v to 5.2v 5vsus 10 this should be used as power source that stores the brightness/contrast values & the circuit that interfaces with smb_clk & smb_dat 5v typ 5valw 9 smbus interface for sending brightness & contrast information to the inverter/panel (0v,5v)typ smb_dat 8 smbus interface for sending brightness & contrast information to the inverter/panel (0v,5v)typ smb_clk 7 control signal input into the inverter to turn the backlight on & off (3.3v-on,0v-off) (0,3.3v)typ fpvee 6 nc 5 "1" open panel_id3 4 "0" connect to gnd panel_id2 3 "1" open panel_id1 2 "1" open panel_id0 1 * function pin 52207-1690 ( ffc/fpc) molex description typical(typ) voltage levels input connector note(*) : molex connector no.1 mark engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 22/34
5.7 inverter signal electrical characteristics electrical specifications [hz] 164 160 156 fb burst frequency [khz] 66 59 52 f lamp frequency off [v] 0.8 fpvee on [v] 2.0 fpvee on/off [mw] 25 5 p(5valw) [mw] 25 15 p(5vsus) smdata=0ffh pwr_src=14.4[v] [w] 1.4 1.0 smdata=00h pwr_src=14.4[v] [w] 6.2 5.6 p(pwr_src) input power [v] 5.2 5.0 4.85 5vsus, 5valw ta=25[deg. c] [v] 21 14.4 9.0 pwr_src input voltage condition units max. typ. min. symbol item dimming 1.7 (*1) 7.5 (*1) 9 5 2 ffh 6.5 (*1) 150 (*1) - 100 - 00h max. typ. min. lamp current (return side)[ma] brightness (center) [cd/m 2 ] brightness [%] smdata *1 : reference only smbus data 100 0101 device address device identifier smbus engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 23/34
the following chart is the luminance versus the smbus data for your reference. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 24/34
6.0 pixel format image following figure shows the relationship of the input signals and lcd pixel format image . even and odd pair of rgb data are sampled at a time. r g b r g b r g b r g b r g b r g b r g b r g b even odd even odd 0 1 1599 1st line 1200th line 1598 engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 25/34
7.0 interface timings 7.1 timing characteristics (vesa uxga mode) [dots] 1600 n data even/odd +data [usec] 9.877 thd display +dsptmg [tck] 32 8 thf h-front porch [tck] 511 152 8 thb h-back porch [tck] 255 96 8 tha [usec] 1.185 tha h-active level [tck] 2047 1080 1024 nh [usec] 13.33 th [khz] 75.0 fh scan rate +h-sync [lines] 1200 m v-line +dsptmg [lines] 125 1 1 nvf v-front porch [lines] 125 46 6 nvb v-back porch [lines] 63 3 1 nva [us] 839.8 40.0 13.33 tva v-active level [lines] 2046 1250 1208 nv [ms] 16.67 tv [hz] 60.0 fv frame rate +v-sync [ns] 13.3 12.3 12.0 tck [mhz] 83.0 81.0 75.0 fdck freqency dtclk unit max. typ. min. symbol item signal note1 : both positive hsync and positive vsync polarity is recommended. note2 : when there are invalid timing, display appears black pattern. synchronous signal defects and enter auto refresh for lcd module protection mode. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 26/34
(vesa uxga fpt mode) [dots] 1600 n data even/odd +data [usec] 12.053 thd display +dsptmg [tck] 48 8 thf h-front porch [tck] 511 56 8 thb h-back porch [tck] 255 8 8 tha [usec] 0.121 tha h-active level [tck] 1023 912 873 nh [usec] 13.74 th [khz] 73.0 fh scan rate +h-sync [lines] 1200 m v-line +dsptmg [lines] 125 12 3 nvf v-front porch [lines] 125 1 1 nvb v-back porch [lines] 63 1 1 nva [us] 13.7 13.7 tva v-active level [lines] 2046 1214 1208 nv [ms] 16.67 tv [hz] 60.0 fv frame rate +v-sync [ns] 16.4 15.1 14.5 tck [mhz] 69.0 66.4 61.0 fdck freqency dtclk unit max. typ. min. symbol item signal note1 : both positive hsync and positive vsync polarity is recommended. note2 : when there are invalid timing, display appears black pattern. synchronous signal defects and enter auto refresh for lcd module protection mode. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 27/34
(vesa uxga mode) typical vertical timing table 0.613 ms (46 lines) 0.040 ms (3 lines) 16.667 ms (1250 lines) 0.013 ms (1 line) 16.000 ms (1200 lines) 0.667 ms (50 lines) 1600 x 1200 at 60hz (h line rate : 13.3 us) tvb vsync back porch tva vsync width tv,nv frame time tvf vsync front porch m active field tvblk vertical blanking support mode typical horizontal timing table 1.877 us (304 dots) 1.185 us (192 dots) 13.333 us (2160 dots) 0.395 us (64 dots) 9.877 us (1600 dots) 3.457 us (560 dots) 1600 x 1200 dotclock : 162.000 mhz (81.000mhz x2) thb hsync back porch tha hsync width th,nh h line time thf hsync front porch thd active field thblk horizontal blanking support mode (vesa uxga fpt mode) typical vertical timing table 0.014 ms (1 line) 0.014 ms (1 line) 16.632 ms (1214 lines) 0.164 ms (12 line) 16.440 ms (1200 lines) 0.192 ms (14 lines) 1600 x 1200 at 60hz (h line rate : 13.7 us) tvb vsync back porch tva vsync width tv,nv frame time tvf vsync front porch m active field tvblk vertical blanking support mode typical horizontal timing table 0.844 us (112 dots) 0.121 us (16 dots) 13.740 us (1824 dots) 0.723 us (96 dots) 12.053 us (1600 dots) 1.687 us (224 dots) 1600 x 1200 dotclock : 132.75 mhz (66.375mhz x2) thb hsync back porch tha hsync width th,nh h line time thf hsync front porch thd active field thblk horizontal blanking support mode engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 28/34
7.2 timing definition tvblk m tvf tva tvb tv dsptmg -vsync +vsync thblk thd thf tha thb th dsptmg -hsync +hsync 0 2 4 n-4 n-2 video(even) video(odd) video(even) video(odd) dtclk 1 3 5 n-3 n-1 tck engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 29/34
8.0 power consumption input power specifications are as follows; [mvp-p] 100 allowable logic/lcd drive ripple noise vddns [mvp-p] 100 allowable logic/lcd drive ripple voltage vddrp all black pattern, vdd=3.3[v] [ma] 730 vdd current idd max pattern, vdd=3.0[v] [ma] 940 vdd current idd all black pattern, vdd=3.3[v] [w] 2.4 vdd power pdd max. pattern, vdd=3.6[v] [w] 3.4 vdd power pdd load capacitance 68uf [v] 3.6 3.3 3.0 logic/lcd drive voltage vdd condition units max typ min parameter symbol max. pattern : 2dot vertical sub-pixel stripe. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 30/34
9.0 power on/off sequence vdd power and lamp on/off sequence is as follows. interface signals are also shown in the chart. signals from any system shall be hi-z state or low level when vdd is off. 90% 10% 10% 10% 90% 10ms max. 0 min. 0 v 0 v vdd signals 180ms min. 0 min. 0 v pwr_src 10% 10% 150ms min. 100ms min. 20ms min. fpvee 5valw/5vsus 0 v 0 v 1ms min. 30ms max. 10ms min. 0ms min. 90% 90% 90% 90% 90% 90% 10% 10% 10% 10% 0ms min. 0ms min. 0ms min. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 31/34
10.0 mechanical characteristics engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 32/34
engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 33/34
11.0 national test lab requirement the display module is authorized to apply the ul recognized mark. conditions of acceptability this component has been judged on the basis of the required spacings in the standard for safety of information technology equipment, including electrical business equipment, can/csa c22.2 no.950-95 *ul 1950, third edition, including revisions through revision date march 1,1998, which are based on the fourth amendment to iec 950, second edition, which would cover the component itself if submitted for listing. the inverter output circuit supplied with this model is a limited current circuit. the units are supplied by limited power sources. the terminals and connectors are suitable for factory wiring only. the terminals and connectors have not been evaluated for field wiring. a suitable electrical and fire enclosure shall be provided. ****** end of page ****** engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. february 1,2002 oem i-97h-03 34/34

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